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[VHDL-FPGA-Verilog] DDR_SDRAM_verilog

Description: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
Platform: | Size: 752640 | Author: 宋珂 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[Other] DDR_allegro

Description: 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
Platform: | Size: 372736 | Author: 朱宝军 | Hits:

[Software Engineering] 20060510191318991

Description: ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
Platform: | Size: 2253824 | Author: 盛雪飞 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: 利用fpga读写ddr的源代码 实测可以使用-Ddr use FPGA to read and write the source code can use the measured
Platform: | Size: 474112 | Author: 朱宝军 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAMControllerverilogcode

Description: 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller, of course, have the test module.
Platform: | Size: 477184 | Author: fdasfds | Hits:

[Communication-Mobile] DDR_interface

Description: 高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 7. 编译并查看编译结果 -High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS generated module 3. Have a DQ module 4. Have a PLL module 5. Copies of the above steps to generate a document to a subdirectory 【Project】 6. Open the subdirectory 【Project】 DataPath.qpf in engineering, design top-level module 7. compilers to compile the results and see
Platform: | Size: 28672 | Author: 田文军 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: DDR SDRAM的veilog hdl程序，经过验证 效果不错-DDR SDRAM' s veilog hdl procedures, good results verified
Platform: | Size: 475136 | Author: 寒心雪林 | Hits:

[VHDL-FPGA-Verilog] 512Mb_ddr_Modules

Description: DDR and DDR DIMM Controller
Platform: | Size: 23552 | Author: starplus | Hits:

[VHDL-FPGA-Verilog] SouceCode_0f_DDR_SDRAM_Controller_by_VHDL

Description: VHDL语言编写的DDR RAM控制器的源码。-VHDL language source controller DDR RAM.
Platform: | Size: 683008 | Author: SYQ | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
Platform: | Size: 678912 | Author: liujie | Hits:

[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl

Description: DDR SDRAM控制器的VHDL代码已经测试-DDR SDRAM controller VHDL code
Platform: | Size: 13312 | Author: tom | Hits:

[Other] yuqix_datum

Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。 debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考 RTL Coding and Optimization Guide for use with Design Compiler.pdf 数提讲座（1）.wmv 数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。 ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。 基于DDR SDRAM控制时序分析的模型.pdf 全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。 数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真. -i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference. debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference RTL Coding and Optimization Guide for use with Design Compiler.pdf Mention the number of lectures (1). Wmv Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look. ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese . DDR SDRAM control the timing analysis based on the model. Pdf
Platform: | Size: 20989952 | Author: 喻琪 | Hits:

[VHDL-FPGA-Verilog] DDR_controller_verilog

Description: ddr的控制程序，用verilog实现的，非常的具体。-ddr
Platform: | Size: 623616 | Author: 张杰 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_VHDL

Description: 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM VHDL的模型；simulation包含VHDL测试平台、modelsim工程文、设计 库函数；source包含vhdl源文件；synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test bench, modelsim project text, design library function source contains the vhdl source file synthesis comprehensive document that contains the project.
Platform: | Size: 886784 | Author: 陈少华 | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_V1_1

Description: DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device
Platform: | Size: 37888 | Author: jordanliang | Hits:

[SCM] DDR2SDRAM

Description: 使用MIG工具生成DDR控制器的技术介绍-Using the MIG tool to generate the DDR Controller Technology
Platform: | Size: 10240 | Author: 林果 | Hits:

[source in ebook] xapp702

Description: 用Virtex4系列FPGA实现DDR控制器的技术介绍-With Virtex4 series FPGA to achieve DDR Controller Technology
Platform: | Size: 216064 | Author: 林果 | Hits:

[VHDL-FPGA-Verilog] ddr2_controller

Description: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Platform: | Size: 52224 | Author: yanxp | Hits:
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